In general, an artificial neural network (ANN) can use a network of neurons to process inputs to the network and to generate outputs from the network. Each neuron m in the network can receive a set of inputs pk, where k=1, 2, . . . , n. In general, some of the inputs to a neuron may be the outputs of certain neurons in the network; and some of the inputs to a neuron may be the inputs to the network as a whole. The input/output relations among the neurons in the network represent the neuron connectivity in the network. Each neuron m can have a bias bm, an activation function fm, and a set of synaptic weights wmk for its inputs pk respectively, where k=1, 2, . . . , n. Different neurons in the network may have different activation functions. Each neuron m can generate a weighted sum sm of its inputs and its bias, where sm=bm+wm1×p1+wm2×p2+ . . . +wmn×pn. The output am of the neuron m can be the activation function of the weighted sum, where am=fm (sm). The relations between the input(s) and the output(s) of an ANN in general can be defined by an ANN model that includes the data representing the connectivity of the neurons in the network, as well as the bias bm, activation function fm, and synaptic weights wmk of each neuron m. Using a given ANN model a computing device can compute the output(s) of the network from a given set of inputs to the network.
A 3D IC is an integrated circuit built by stacking silicon dies and interconnecting them vertically so that a combination of the dies is a single device. With a 3D IC, electrical paths through the device can be shortened by its vertical layout, which creates a device that can be faster and has a smaller footprint than similar ICs arranged side-by-side. 3D ICs can be generally grouped into 3D SICs, which refers to stacked ICs with through-silicon via interconnects (TSVs), and monolithic 3D ICs, which are generated using fabrication processes to realize 3D interconnects at the local levels of the on-chip wiring hierarchy as set forth by the International Technology Roadmap for Semiconductors (ITRS). Using the fabrication processes to realize the 3D interconnects can produce direct vertical interconnects between device layers. Monolithic 3D ICs are built in layers on a single wafer that is diced into separate 3D ICs.
3D SICs can be produced by three known general methods: a die-to-die, die-to-wafer, or a wafer-to-wafer method. In a die-to-die method, electronic components are generated on multiple dies. Then, the dies are aligned and bonded. A benefit of a die-to-die method is that each die can be tested before aligned and bonded with another die. In a die-to-wafer method, electronic components are generated on multiple wafers. One of the wafers can be diced and then aligned and bonded on to die sites of another wafer, accordingly. In a wafer-to-wafer method, electronic components are generated on multiple wafers, which are then aligned, bonded, and diced into separate 3D ICs.
A TSV is a vertical electrical connection that can pass through a die. TSVs can be a central part to increasing performance in 3D packages and 3D ICs. With TSVs, compared to alternatives for connecting stacked chips, the interconnect and device density can be substantially higher, and the length of the connections can be shorter.